Description: Adiabatic Logic by Philip Teichmann Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. FORMAT Paperback LANGUAGE English CONDITION Brand New Publisher Description Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design. Back Cover Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design. Author Biography Philip Teichmann studied electrical engineering at the Technische Universität MÜnchen with a focus on the physics of electronic devices and microelectronics. During his work at the Institute of Technical Electronics at the Technische Univeristät MÜnchen he focused on the design of circuits for ultra low-power energy consumption. He has authored and co-authored several papers on Adiabatic Logic and presented his work at international conferences. Table of Contents 1 Introduction. 2 Fundamentals of Adiabatic Logic. 3 Future trend in Adiabatic Logic. 4 Generation of the power-clock. 5 Power-Clock Gating. 6 Arithmetic structures in Adiabatic Logic. 7 Measurement results of an adiabatic FIR filter. 8 Conclusions. Feature This is the first comprehensive book on Adiabatic Logic systems It presents how Adiabatic Logic will perform with future scaling, future devices and degrading effects It presents measurement results of a manufactured adiabatic system and compares it to static CMOS Design methodology is presented to generate more energy efficient and less area consuming adiabatic digital signal processing units Details ISBN9400737270 Author Philip Teichmann Publisher Springer Language English ISBN-10 9400737270 ISBN-13 9789400737273 Media Book Format Paperback Short Title ADIABATIC LOGIC 2012/E Pages 166 Series Springer Series in Advanced Microelectronics DEWEY 621.395 Series Number 34 Year 2013 Imprint Springer Subtitle Future Trend and System Level Perspective Place of Publication Dordrecht Country of Publication Netherlands Edition 2012th Publication Date 2013-11-29 Edition Description 2012 ed. Alternative 9789400723443 Audience Professional & Vocational Illustrations XVIII, 166 p. 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ISBN-13: 9789400737273
Book Title: Adiabatic Logic
Number of Pages: 166 Pages
Language: English
Publication Name: Adiabatic Logic: Future Trend and System Level Perspective
Publisher: Springer
Publication Year: 2013
Subject: Engineering & Technology, Computer Science, Physics
Item Height: 235 mm
Item Weight: 290 g
Type: Textbook
Author: Philip Teichmann
Subject Area: Material Science
Item Width: 155 mm
Format: Paperback
