Description: Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Embedded Systems by Filip Thoen, Francky Catthoor Estimated delivery 3-12 business days Format Hardcover Condition Brand New Description system is a complex object containing a significant percentage of elecĀ A tronics that interacts with the Real World (physical environments, humans, etc. Publisher Description The combination of VLSI process technology and real-time digital signal processing (DSP) has brought a break-through in information technology. This rapid technical revolution allows the integration of ever more complex systems on a single chip. However, these technology and integration advances have not been matched by an increase in design productivity, causing technology to leapfrog the design of integrated circuits (ICs). The success of these emerging "systems-on-a-chip" (SOC) can only be guaranteed by a systematic and formal design methodology, possibly automated in computer-aided design (CAD) tools, and effective re-use of existing intellectual property (IP). In this book, a contribution is made to the modelling, timing verification and analysis, and the automatic synthesis of integrated real-time DSP systems. This text gives a comprehensive overview of existing techniques. The emphasis throughout is on the support and guaranteeing of the real-time aspect and constraints of these systems, which avoids time consuming design iterations and safeguards the ever shrinking time-to-market.The proposed "Multi-Thread Graph" (MTG) system model features two-layers, unifying a (timed) Petri net and a control-data flow graph. Its unique interface between both models offers the best of two worlds and introduces an extra abstraction level hiding the operation-level details which are unnecessary during global system exploration. The formulated timing analysis and verification approach supports the calculation of temporal separation between different MTG entities as well as realistic performance metrics for highly concurrent systems. The synthesis methodology focuses on managing the task-level concurrency (i.e. task scheduling), as part of a proposed overall system design meta flow. It emphasizes performance and timing aspects ("timeliness"), while minimizing processor cost overhead as driven by high-level cost estimators. The approach is new in the abstraction level it employs, and in its optimal hybrid dynamic/static scheduling policy which, driven by coestimators, selects the scheduling policy for each behaviour. At the low-level, RTOS synthesis generates an application-specific scheduler for the software component.The proposed synthesis methodology (at the task-level) is asserted to yield most optimal results when employed before the hardware/software partition is made. At this level, the distinction between these two is minimal, such that all steps in the design trajectory can be shared, thereby reducing the system cost significantly and allowing tighter satisfaction of timing/performance constraints. Details ISBN 0792377370 ISBN-13 9780792377375 Title Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Embedded Systems Author Filip Thoen, Francky Catthoor Format Hardcover Year 1999 Pages 438 Edition 2000th Publisher Springer GE_Item_ID:158829966; About Us Grand Eagle Retail is the ideal place for all your shopping needs! With fast shipping, low prices, friendly service and over 1,000,000 in stock items - you're bound to find what you want, at a price you'll love! Shipping & Delivery Times Shipping is FREE to any address in USA. Please view eBay estimated delivery times at the top of the listing. Deliveries are made by either USPS or Courier. We are unable to deliver faster than stated. International deliveries will take 1-6 weeks. NOTE: We are unable to offer combined shipping for multiple items purchased. This is because our items are shipped from different locations. Returns If you wish to return an item, please consult our Returns Policy as below: Please contact Customer Services and request "Return Authorisation" before you send your item back to us. Unauthorised returns will not be accepted. Returns must be postmarked within 4 business days of authorisation and must be in resellable condition. Returns are shipped at the customer's risk. We cannot take responsibility for items which are lost or damaged in transit. For purchases where a shipping charge was paid, there will be no refund of the original shipping charge. Additional Questions If you have any questions please feel free to Contact Us. Categories Baby Books Electronics Fashion Games Health & Beauty Home, Garden & Pets Movies Music Sports & Outdoors Toys
Price: 188.92 USD
Location: Fairfield, Ohio
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ISBN-13: 9780792377375
Book Title: Modeling, Verification and Exploration of Task-Level Concurrency
Number of Pages: Xv, 438 Pages
Language: English
Publication Name: Modeling, Verification, and Exploration of Task-Level Concurrency of Real-Time Embedded Systems
Publisher: Springer
Subject: Systems Architecture / General, Cad-Cam, Electrical, Data Processing
Publication Year: 1999
Type: Textbook
Item Weight: 63.5 Oz
Item Length: 9.3 in
Subject Area: Computers, Technology & Engineering
Author: FiLIP Thoen, Francky Catthoor
Item Width: 6.1 in
Format: Hardcover